Modern digital integrated circuits such as central processing units (CPUs) are typically capable of operating with several different clock frequencies. Assume that a CPU can reduce its clock frequency while still meeting the processing requirements of an application that is running on the CPU. As is well known, a reduction in the clock frequency of the CPU proportionally reduces the CPU power consumption. With a lower clock frequency less power is consumed because there are fewer signal level changes within a given time period.
As is also well known, the power consumption of a digital circuit is quadratically proportional to the operating voltage. Therefore, decreasing the voltage level of the operating voltage (i.e., the supply voltage) and reducing the clock frequency can provide significant power savings in a digital circuit.
Dynamic Voltage Scaling (DVS) is a power management technique in which pre-determined voltage values (within a voltage table) are used for each requested operating clock frequency of a CPU. The voltage levels that are defined in the voltage table must be carefully selected in order to adequately cover all process and temperature corners so that the CPU will function correctly at each clock frequency.
Adaptive Voltage Scaling (AVS) is a power management technique in which the supply voltage of a digital integrated circuit is adjusted automatically. The supply voltage is adjusted using closed loop feedback to a minimum level that is required for the proper operation of the integrated circuit at a given clock frequency.
The major difference between Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling (AVS) is that the Adaptive Voltage Scaling (AVS) automatically measures variation of the process and temperature in order to balance the supply voltage and system delay (digital cell delay) that is due to closed loop feedback. This means that the supply voltage in the AVS system is automatically reduced at lower temperatures and for faster silicon. As the supply voltage is reduced, the power consumption is also reduced.
FIG. 1 illustrates a block diagram of an embodiment of an exemplary prior art Adaptive Voltage Scaling (AVS) system 100. AVS system 100 comprises a System-on-a-Chip (SoC) unit 110 and an Energy Management Unit (EMU) 120. The System-on-a-Chip (SoC) unit 110 comprises a Clock Management Unit (CMU) 130, a Variable Voltage Domain CPU System 140, a Hardware Performance Monitor (HPM) 150, and an Advanced Power Controller (APC) 160. The Hardware Performance Monitor (HPM) 150 is located within the Variable Voltage Domain CPU System 140.
The Clock Management Unit (CMU) 130 receives a system clock signal from a system clock unit (not shown in FIG. 1). The Clock Management Unit (CMU) 130 provides clock frequencies for the central processing unit (CPU) (also not shown in FIG. 1). The Clock Management Unit (CMU) 130 also provides clock frequencies for the Hardware Performance Monitor (HPM) 150. The clock frequencies that are provided to the Hardware Performance Monitor (HPM) 150 are represented by the designation HPM CLOCK.
The Hardware Performance Monitor (HPM) 150 tracks gate delays in the current operational conditions. The CPU system and the Hardware Performance Monitor (HPM) 150 are in the Variable Voltage Domain CPU System 140. The Hardware Performance Monitor (HPM) 150 outputs a performance code to the Advanced Power Controller (APC) 160. The performance code indicates the propagation delay of digital gate cells. The Advanced Power Controller (APC) 160 processes the delay data and requests appropriate changes to the supply voltage.
The Advanced Power Controller (APC) 160 is coupled to and communicates with the Energy Management Unit (EMU) 120. In one embodiment the coupling between the Advanced Power Controller (APC) 160 and the Energy Management Unit (EMU) 120 is a PowerWise® interface (PWI). The mark PowerWise® is a registered trademark of the National Semiconductor Corporation. The Advanced Power Controller (APC) 160 sends a request to the Energy Management Unit (EMU) 120 to change the supply voltage. The Energy Management Unit (EMU) 120 provides the requested supply voltage level to the System-on-a-Chip (SoC) 110. The adjustable supply voltage from the Energy Management Unit (EMU) 120 is designated VAVS in FIG. 1.
The operating system of a modern central processing unit (CPU) may support a real time scheduling of performance levels. Each performance level may have associated with it a specific value of operating clock frequency. The operating system is capable of selecting an operating clock frequency for which the CPU performance is minimized on a real time basis and for which the deadlines of a particular application are still met. For example, while an MPEG4 movie encoding application is running, a performance scheduling algorithm of the operating system may predict and change the performance level of the CPU in ten millisecond (10 ms) intervals.
The Hardware Performance Monitor (HPM) 150 tracks gate delays in the current operational conditions. The Hardware Performance Monitor (HPM) 150 outputs a performance code to the Advanced Power Controller 160. The performance code indicates the propagation delay of digital gate cells. In particular, Hardware Performance Monitor (HPM) 150 sends the performance code to the Advanced Power Controller 160. The Advanced Power Controller 160 then subtracts the performance code from a standard Reference Calibration Code (RCC) to obtain an error signal.
The error signal is referred to as “Slack Time”. The Slack Time error signal comprises a digital error signal in a two's complement number format. If the Slack Time is positive an increase in voltage is required. If the Slack Time is negative a decrease in voltage is required. The Slack Time error signal is provided to a Compensation Unit (not shown) within the Advanced Power Controller 160. Based on the value of the Slack Time error signal, the Compensation Unit sends a signal to the Energy Management Unit (EMU) 120 to cause the Energy Management Unit (EMU) 120 to adjust the value of the adjustable output voltage (VAVS) of Energy Management Unit (EMU) 120.
Modern System-on-a-Chip (SoC) digital logic circuits may consume large amounts of power both in terms of leakage power and dynamic power. Leakage power is the power that is consumed when no switching activity occurs within the logic circuitry. Dynamic power is the power that is consumed by the logic circuitry to alter its internal states (e.g., charging and discharging internal nodes).
In deep-submicron complementary metal oxide semiconductor (CMOS) processes it is known that the leakage power represents a significant amount of power consumption in System-on-a-Chip (SoC) digital logic circuitry. Therefore, it is highly desirable to be able to minimize the leakage power that is consumed. The leakage power in a logic circuit such as a NAND circuit or a NOR circuit depends upon the physical properties of the transistors that are used to implement the logic circuit.
To a first order approximation the threshold voltage (VT) of a transistor determines the leakage properties of a transistor. The greater the threshold voltage VT of a transistor, the lower the leakage power that is consumed by the transistor. The relationship between the threshold voltage VT and the leakage power is exponential. This feature gives high threshold voltage transistors (high VT) much lower leakage than those transistors with a low threshold voltage (low VT).
Unfortunately, the speed of logic circuitry that is implemented with high VT transistors is less than the speed of logic circuitry that is implemented with low VT transistors. The speed of the logic circuitry and the leakage power properties must be traded off against each other in System-on-a-Chip (SoC) design.
In a complex System-on-a-Chip (SoC) there are hundreds of thousands of logic signal paths between storage elements such as latches and flip-flops. For a complex System-on-a-Chip (SoC) system to operate at a given clock frequency all signals have to propagate across the combinatorial logic between the storage elements in one clock cycle.
Because there are large numbers of logic paths it is also natural that not all paths are equal. The logic function of a path may be simple and require only a few gates. This type of path will be particularly fast. Other types of paths may be quite complex and consume a great deal of time. These types of paths will be particularly slow. The long (and slow) paths are called “critical paths” because the delay through them defines the maximum clock speed of the System-on-a-Chip (SoC) and therefore the quality of performance of the chip.
Modern synthesis tools take advantage of the fast paths that exist in an integrated circuit design by slowing them down by replacing fast high-leakage logic circuits (that have low VT) with slow low-leakage logic circuits (that have high VT). In this manner the average leakage power in an integrated circuit design is reduced without reducing the maximum performance of the design (which is still defined by the critical paths implemented with the fast high-leakage logic circuits).
The implementation of a System-on-a-Chip (SoC) integrated circuit design that reduces the average leakage power in the manner described uses both low VT components and high VT components. This type of implementation comprises (1) some logic paths that are “critical” and that contain only fast, low VT logic circuitry, and (2) some logic paths that are “least critical” and that contain only slow, high VT logic circuitry, and (3) some logic paths that contain both fast, low VT logic circuitry and slow, high VT logic circuitry.
When a closed loop adaptive voltage scaling system of the type illustrated in FIG. 1 minimizes the supply voltage, both the dynamic power and the leakage power are minimized. The expression for the power of the System-on-a-Chip (Soc) is given by the expression:P=αCV2fCLK+VIL  Eq. (1)
P is the total power of the SoC. Alpha (α) is a switching activity factor. Alpha (α) represents the percentage of nodes that are switching at each clock cycle. C is the node capacitance inside the SoC. The expression fCLK is the SoC clock frequency. V is the supply voltage. The expression IL is the leakage current. Equation (1) assumes rail-to-rail switching for the CMOS logic.
As previously described, Hardware Performance Monitor (HPM) 150 shown in FIG. 1 produces an output code that is relative to the propagation speed of the signals inside the logic of the System-on-a-Chip (SoC) 110. FIG. 2 illustrates one possible prior art implementation 200 of the Hardware Performance Monitor (HPM) 150. This implementation 200 comprises a ring oscillator 210 and a counter 220. The ring oscillator 210 provides an output clock signal to the counter 220. The counter 220 receives a sample and reset signal and generates a sensor output signal.
FIG. 3 illustrates another possible prior art implementation 300 of the Hardware Performance Monitor (HPM) 150. This implementation 300 comprises a tapped delay line that comprises a signal source 310, a plurality of logic elements (320a, 320b, 320c) and a sample and code output word unit 330. The logic elements (320a, 320b, 320c) provide input to the sample and code output word unit 330. The sample and code output word unit 330 receives a sample signal and generates a sensor output signal.
The ring oscillator implementation 200 of the Hardware Performance Monitor (HPM) 150 is able to produce a digital output code that is relative to the speed of the logic that is used to implement the ring oscillator implementation 200. The tapped delay line implementation 300 of the Hardware Performance Monitor (HPM) 150 is able to produce a digital output code that is relative to the speed of the logic that is used to implement the tapped delay line implementation 300.
In both types of implementation of the Hardware Performance Monitor (HPM) 150 several factors affect the output from the Hardware Performance Monitor (HPM) 150. These factors include the semiconductor manufacturing process, the logic library that is used, the die temperature and the supply voltage. It is possible to use either implementation 200 or implementation 300 (or both) to implement Hardware Performance Monitor (HPM) 150 (and an adaptive voltage scaling system) of the type shown in FIG. 1.
In a conventional adaptive voltage scaling system, the arrangement that is shown in FIG. 1 works very well. All logic is implemented with a standard logic cell library having a single threshold voltage VT level for all of the PMOS transistors and all of the NMOS transistors. For convenience of description we will refer to this conventional arrangement as a single VT library and the resulting design as a single VT design.
In a single VT design all signal paths consist of logic cells from the single VT library. When the supply voltage of the logic is changed, the delay of all the logic cells is changed by the same fraction. For example, a logic path with two successive inverters will have twice the delay compared to a logic path with a single inverter (assuming the same drive and the same load for the inverters). It is possible to describe the frequency-optimal supply voltage characteristic of a System-on-a-Chip (SoC) with a single curve. In addition, in a single VT design, process and temperature variation maintain the relative relationships between different delay paths.
In a design that has a plurality of VT domains (often referred to as a multi VT design), the relationship of the various logic paths is much more complex. Because different logic paths may contain logic cells from different libraries, the behavior of each VT library across the supply voltage affects the delay behavior of each logic path differently.
The delay of a logic cell is related to the threshold voltage VT of the transistors inside the logic cell in a non-linear manner. The logic cells with high VT transistors will have a much larger relative delay increase with the same amount of supply voltage change than the same logic cell when implemented with low VT transistors. For this reason one can no longer claim that the delay of an inverter is always half of the delay of two consecutive inverters if the inverters are from different VT logic libraries.
FIG. 4 illustrates a graph 400 of supply voltage (V) versus operating frequency in megaHertz (MHz) for a dual VT design. A dual VT design is a multi VT design that has two values of VT. The first VT value is designated as the low VT value and the second value of VT is designated as the high VT value.
The letters “DFS” in the expression “DFS frequency” in FIG. 4 stand for Dynamic Frequency Scaling. The voltage-frequency characteristics of a dual VT design (that has both low VT logic cells and high VT logic cells) can be bounded by two curves. The upper curve 410 represents the high VT transistor logic curve and the lower curve 420 represents the low VT transistor logic curve.
If the design used only high VT logic, then the upper curve 410 would completely characterize the design. If the design used only low VT logic, then the lower curve 420 would completely characterize the design. The behaviors of all of the “mixed” paths inside the design are between the upper curve 410 and the lower curve 420.
It is important to note that the upper curve 410 and the lower curve 420 intercept at a point that is designated as the “design target point”. The design target point is typically the slow-slow corner fro both high VT and low VT. This is the operating voltage at which the System-on-a-Chip (SoC) is designed to operate at a certain frequency. The synthesis and timing analysis tools will balance all logic paths at this frequency so all critical high VT and low VT paths are equal. But as soon as the voltage (and frequency) is decreased, the difference between the two VT logic libraries becomes apparent.
Additional complexity is introduced by process and temperature variation on the System-on-a-Chip (SoC). Manufacturing inaccuracies may cause shifts in the VTs of a logic library. In addition, ambient temperature differences and System-on-a-Chip (SoC) self heating may cause temperature changes on the die. Both of these mechanisms may cause variation in the characteristic curves of the design. FIG. 5 shows the impact of process variation on a dual VT System-on-a-Chip (SoC) design.
FIG. 5 illustrates a graph 500 of supply voltage (V) versus operating frequency in megaHertz (MHz) for a dual VT design. FIG. 5 illustrates how much change is needed to compensate for the process and temperature variance of high VT logic paths and low VT logic paths at each operating frequency (clock frequency).
The upper curve 510 represents the high VT transistor logic curve. The dotted lines (520 and 530) on the sides of curve 510 illustrate how much change is needed to compensate for the process and temperature variance of the high VT logic paths. The lower curve 540 represents the low VT transistor logic curve. The dotted lines (550 and 560) on the sides of curve 540 illustrate how much change is needed to compensate for the process and temperature variance of the low VT logic paths.
The presently existing adaptive voltage scaling (AVS) approach is well adapted to handle a single logic library with a single VT and consistent behavior in a System-on-a-Chip (SoC). The problem is that a modern System-on-a-Chip (SoC) may have a plurality of logic cell libraries with different VTs. Therefore, there is no single characteristic curve for all of the logic paths. There is no single Hardware Performance Monitor (HPM) that could model the System-on-a-Chip (SoC) for the Advanced Power Controller (APC). The situation is especially complex near the “design target point” where any cell library (regardless of its VT) may form the “critical path” in some process corner.
A Hardware Performance Monitor (HPM) that has a mixed construction (i.e. some logic cells from all different VT libraries) would not solve the problem. This is because such a Hardware Performance Monitor (HPM) would only average the characteristic curves of the libraries and would not accurately predict any actual operating points for the System-on-a-Chip (SoC).
Therefore, there is a need in the art for a system and method that is capable of efficiently providing an accurate adaptive voltage scaling (AVS) system for a System-on-a-Chip (SoC) that operates with a plurality of threshold voltage VT logic libraries.